
Accelerating Binary String Comparisons with a Scalable, Streaming-Based System Architecture Based on FPGAs
In: Algorithms, Vol. 13 Issue 2
Acceleration of the SPADE Method Using a Custom-Tailored FP-Growth Implementation
In: Frontiers in Neuroinformatics, Vol. 15 Issue 15







Binary Associative Memories as a Benchmark for Spiking Neuromorphic Hardware
In: Frontiers in Computational Neuroscience, Vol. 11





CoreVA-MPSoC: A Many-core Architecture with Tightly Coupled Shared and Local Data Memories
In: IEEE Transactions on Parallel and Distributed Systems, Vol. 29 Issue 5, page 1030-1043



