
Accelerating Binary String Comparisons with a Scalable, Streaming-Based System Architecture Based on FPGAs
In: Algorithms, Vol. 13 Issue 22020
Acceleration of the SPADE Method Using a Custom-Tailored FP-Growth Implementation
In: Frontiers in Neuroinformatics, Vol. 15 Issue 152021






An associative memory with neural architecture and its VLSI implementation
In: Proceedings of the twenty-fourth annual Hawaii International Conference on System Sciences / Hawaii International Conference on System Sciences <24, 1991, Kauai, Hawaii>, Vol. 1, page 212-2182009


Binary Associative Memories as a Benchmark for Spiking Neuromorphic Hardware
In: Frontiers in Computational Neuroscience, Vol. 112017





CoreVA-MPSoC: A Many-core Architecture with Tightly Coupled Shared and Local Data Memories
In: IEEE Transactions on Parallel and Distributed Systems, Vol. 29 Issue 5, page 1030-10432018

