During the long shutdown LS3 when the LHC will be upgraded to the HL-LHC, the inner tracker of the ATLAS experiment at the LHC will be replaced. This also includes the innermost part of ATLAS, the pixel detector. The goal is to collect 3000/fb with this detector. To ensure a stable and reliable operation for this time (~10 years), there has to be a control system which steers and monitors the detector, similar to the detector control system (DCS) of the current pixel detector. Due to massive changes in the concept of the new pixel detector, the current DCS cannot be reused and a new one is being developed. This new DCS concept for the pixel detector contains three paths, a hard wired interlock path, a diagnostics path integrated into the data acquisition and a control and feedback path for user interactions during operation. In this contribution we describe an improved concept of the control and feedback path, especially designed for the case of a serially powered detector. Though the operation of a parallel powering scheme with DC-DC converters is also possible. The control and feedback path is made up by a network of two nodes: The first node, the DCS controller, is located at the End-of-Stave card at the end of each sub structure (disc or half stave). The second node, the DCS chip, is located on the flex attached to each detector module. To cope with the high radiation levels and the low material budget, these nodes are implemented in custom made ASICs. Communication between these two nodes is transmitted by an I2C bus, which was enhanced with four check bits to provide better reliability. To meet the standards of the ATLAS DCS, the communication from the DCS chip to the DCS computers is realized by a CAN bus. Besides the new concept, the first prototype of the DCS chip the PSPP (Pixel Serial Powering and Protection) chip will be introduced. This chip contains all components, which are foreseen in the concept of the DCS chip. This includes the physical layer for an AC coupled two wire bus, a shunt regulator, a large shunting transistor, an ADC, I2C slave logic and a comparator. The chip has recently been tested and the results will be presented.