Urbina Fuentes, Moisés Ignacio: TIMEA: Time-triggered message-based multicore architecture for AUTOSAR. 2020
Inhalt
- Acknowledgements
- Abstract
- Kurzfassung
- Contents
- List of Figures
- List of Tables
- 1 Introduction
- 2 Background and Basic Concepts
- 2.1 Real-time Embedded Systems
- 2.2 Dependability
- 2.3 Architecture Paradigms in Real-time Systems
- 2.4 AUTOSAR
- 3 Analysis of the State-of-the-Art
- 3.1 AURIX TC3XX
- 3.2 MERASA and parMERASA European Projects
- 3.3 State-of-the-Art of I/O Multicore Solutions
- 3.4 ARINC 653 Health Monitoring
- 3.5 Multicore Approach of AUTOSAR
- 3.6 Limitations of the existing AUTOSAR Multicore Version
- 3.7 Research Gap of the State-of-the-Art
- 4 Message-based Multicore Architecture for AUTOSAR
- 4.1 Overview of the AUTOSAR Multicore System
- 4.2 Architecture of an AUTOSAR Micro-ECU
- 4.3 Architecture of the I/O Gateway Core
- 4.4 Architecture of the Off-Chip Network Gateway Core
- 4.5 Architecture of the Memory Gateway Core
- 4.6 Fault Tolerance Mechanisms
- 5 Simulation Framework for Message-based AUTOSAR MPSoC Platforms
- 5.1 Concept of the Co-simulation Framework
- 5.2 Implementation of the Co-simulation Framework
- 5.3 Extension of the Co-simulation Coordination
- 6 Development Process of TIMEA
- 6.1 Implementation of the AUTOSAR Micro-ECUs
- 6.2 Implementation of the Input/Output Cores
- 6.3 Implementation of the Memory Gateway Core Simulation
- 6.4 Implementation of the Off-Chip Gateway Core
- 7 Evaluation and Results
- 7.1 Evaluation of the Co-simulation Framework for AUTOSAR Message-based MPSoC Platforms
- 7.2 Evaluation of Performance and Fault Containment in AUTOSAR Micro-ECUs
- 7.3 Evaluation of Performance with an I/O Gateway Core
- 7.4 Evaluation of Performance with an Off-chip Network Gateway Core
- 7.5 Evaluation of Performance with a Memory Gateway Core
- 8 Conclusion
- Bibliography
- Selected Publications