Abuteir, Mohammed: Architecture design for distributed mixed-criticality systems based on multi-core chips. 2017
Inhalt
- Kurzfassung
- Abstract
- Contents
- List of Figures
- List of Tables
- 1 Introduction
- 2 Concepts and Terms
- 2.1 Dependability
- 2.2 Fault Hypothesis
- 2.3 Concept of Component, Service and Behavior
- 2.4 Concept of State
- 2.5 Real-Time Systems
- 2.6 Architecture Paradigms
- 2.7 Partitioning
- 2.8 Certification
- 2.9 Modular Certification
- 3 State of the Art in Mixed-Criticality Systems
- 3.1 State of the Art: Communication
- 3.2 State of the Art: Gateways
- 3.3 State of the Art: Distributed Scheduling
- 3.4 Research Gap in the State of the Art
- 4 System Model of Multi-Core Chips Interconnected by Real-Time Ethernet
- 5 Redundancy for Mixed-Criticality Networks with Multiple Ring Topologies
- 6 Off-chip/On-chip Gateways for Mixed-Criticality Systems
- 7 Scheduling of Sporadic and Periodic Traffic in Multi-Cluster Systems
- 8 Implementation and Evaluation
- 9 Conclusion
- Bibliography
- Selected Publications