Owda, Zaher: Predictable transactional memory architecture for hierarchical mixed-criticality systems. 2017
Inhalt
- Abstract
- Kurzfassung
- Table of contents
- List of figures
- List of tables
- 1 Introduction
- 2 Background and Basic Concepts
- 2.1 Real-time Embedded Systems
- 2.2 Dependability
- 2.3 Paradigms of Communication
- 2.4 Memory Technologies and Hierarchy
- 2.5 Transactional Memory
- 3 Analysis of the State-of-the-Art
- 3.1 Requirements for Mixed-Criticality Systems and Transactional Memory Architectures
- 3.2 Architectures and Solutions at Chip Level
- 3.3 Cluster level Distributed Memory Solutions
- 3.4 Research Gaps in the State-of-the-Art
- 4 Transactional Memory Architectures for Mixed-Criticality Systems
- 4.1 TMSoC System Architecture
- 4.2 Hierarchical Transactional Memory Architecture for Distributed MCSs
- 4.3 Fault Hypothesis
- 5 Simulation Framework for Mixed-Criticality Chip Level Architectures
- 5.1 SystemC/TLM MPSoC
- 5.2 DRAMSim2 External Memory
- 5.3 The Mixed-Criticality Transaction Controller (MTC) Implementation
- 5.4 Trace Generation Process
- 6 Simulation Framework for the Hierarchical DTMA
- 7 Evaluation and Results
- 7.1 Evaluation of MCS Framework for Message-based and Shared Memory Interactions
- 7.2 Evaluation of TMSoC
- 7.3 Evaluation of the Hierarchical DTMA
- 8 Conclusion
- References
- List of Acronyms
- Selected Publications