Inhalt

•  
  Introduction
•  
   Overview
•  
  Motivation
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   Subthreshold Design
•  
   Standard Cell Library
•  
   Level Shifter
•  
   Low Power sram
•  
   FDSOI Technology
•  
   Outcomes and Contributions
•  
   Thesis Outline
•  
   Publications
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  Design Space Exploration
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   Multiobjective Optimization
•  
   GAIO
•  
   NSGA-2
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   SPEA2
•  
  Resources
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   Propagation Delay
•  
   Power
•  
   Energy
•  
   Noise Margin
•  
   Area
•  
   Inverter Study
•  
   Level Shifter
•  
   Up level shifter
•  
   Conventional level converter
•  
   State of Art
•  
   cross-coupled pmos
•  
   Current Mirror
•  
  Scale Down Mechanism
•  
   Preliminary Examinations
•  
   Optimization Results
•  
  Proposed Designs
•  
   LVT cell based design in fdsoi technology
•  
   RVT cell based design in fdsoi technology
•  
   Hybrid topology based design in fdsoi technology
•  
   Down Level Converter
•  
  Simulation and Comparison of the Proposed Level Shifter Circuits
•  
  Simulation Results
•  
   Current Mirror Circuits
•  
   Hybrid Topology Circuit
•  
   Performance comparison of the state or art designs
•  
   Supply Voltage and Conversion Range
•  
   Operating Frequency and Propagation Delay
•  
   Switching Energy and Static Power Dissipation
•  
   Chip Area
•  
  Low Power sram
•  
   sram market trend
•  
   Power Reduction Techniques
•  
   Manipulation of supply voltage
•  
   Read/Write Assist Circuitry and Bitline and Wordline Signal Manipulation
•  
   Bitline Leakage Reduction
•  
   Transistor Level Techniques
•  
   Subthreshold Bitcell Design
•  
   Application Specific Techniques
•  
   Operating Principle
•  
  sram Array and associated circuits
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   Address and Data Buffers
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   Row Decoder Design
•  
   Read/Write Column Decoder and Write Driver
•  
   Sense Amplifier
•  
   Control Circuits
•  
   Proposed Design
•  
   Simulation Results
•  
  Subthreshold Library
•  
  Standard Cell Organization
•  
   Physical Design
•  
   Logical Design
•  
   Power Options
•  
   Dimensions
•  
   Design Flow
•  
   Standard-Cell-Based Development Process
•  
   Standard cell library designs
•  
   Low Power Libraries
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  Library Components
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   Combinational Logic
•  
   Sequential Logic
•  
   Clock Tree Elements
•  
   Level Shifter
•  
   Place and Route Cells
•  
   Subthreshold Design Methodology
•  
  Developed Standard Cell Libraries
•  
   65nm cmos Technology
•  
   28nm FDSOI Technology
•  
   Characterization
•  
  Delay Modelling
•  
   Non-linear Delay Model (NLDM)
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   Composite Current Source(CCS)
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   Effective current source model(ECSM)
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   Timing Model
•  
   Power Modelling
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   Liberate Tool Flow
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   Comparison between the two libraries
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  Conclusion and Future Work
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   Conclusion
•  
   Future work
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   List of Figures
•  
   List of Tables
•  
   Acronyms
•  
   Bibliography
•  
   A. Characterization Script
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   B. Datasheet