High-speed clock and data recovery : theory and implementation / by Mohammed Iftekhar ; first reviewer: Prof. Dr.-Ing. J. Christoph Scheytt, second reviewer: Prof. Dr.-Ing. Ahmet Cagri Ulusoy. Paderborn, 2026
Inhalt
- List of Publications
- Zusammenfassung
- Abstract
- Contents
- Introduction
- Analysis and Design
- Transition-based phase detectors
- Modeling of Bang-Bang pll
- Nonlinear time-domain modeling
- Stability factor
- Frequency acquisition
- Extending frequency acquisition range via loop parameters
- Jitter Characterization
- Summary and conclusion
- Automatic Frequency Acquisition using bbpd
- State-of-the-art acquisition techniques
- Novel acquisition technique
- Varactor voltage modulation applied externally to the vco
- Offset current modulation applied within the integral branch
- Spectrum of the recovered clock in steady state
- Summary and conclusion
- Design of High-Speed BBCDRs in SiGe BiCMOS
- SiGe BiCMOS technology overview
- Phase Detection
- Charge Pump + Loop Filter
- Clock generation
- Summary and conclusion
- Design of High-Speed BBCDRs in FD-SOI CMOS
- FD-SOI CMOS technology overview
- Phase Detection
- Charge Pump + Loop Filter
- Clock generation
- Summary and conclusion
- Measurements results
- 28Gbps BBCDR chip in SG25H4 technology
- 28Gbps BBCDR chip in 22FDXTM technology
- 50Gbps BBCDR chip in SG13G3 technology
- Summary and conclusion
- Conclusion and Outlook
- Jitter terminology
- Alexander half-rate NRZ PD and full-rate PAM4 PD
- Transistor characterization and Figures of Merit in FD-SOI CMOS
- Bibliography